Section 16
Sequential logic
Computes SR latch from the circuit model and the stated conditions.
- SR latch sensitive to the Enable level, not an edge; S=R=1 is forbidden.
Computes D latch from the circuit model and the stated conditions.
- D latch transparent while Enable is active (level); it is not clock-edge sampled.
The D flip-flop samples D on the clock edge and holds Q until the next edge.
- Named active edge; obey tsu and th.
Computes JK flip-flop from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.
Computes T flip-flop from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.
Setup time tsu is the window in which D must be stable before the clock edge.
- Named active edge; obey tsu and th.
Hold time th is the window in which D must stay stable after the clock edge.
- Named active edge; obey tsu and th.
Computes n-bit register from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.
Computes Binary counter from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.
Computes Modulo-n counter from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.
Computes Moore machine from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.
Computes Mealy machine from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.
Computes Maximum synchronous frequency from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.
Computes Metastability from the circuit model and the stated conditions.
- Named active edge; obey tsu and th.