Section 14
Logic families and gates
Levels VOH VOL VIH VIL bound valid high and low on the VTC.
- Logic family on a fixed supply; static levels.
NMH=VOH−VIH is the high noise margin between a high output and VIH.
- Logic family on a fixed supply; static levels.
Computes Low noise margin from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.
Computes High-to-low propagation delay from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.
Computes Average propagation delay from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.
Computes Logic fan-out from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.
The CMOS VTC inverts: low Vin yields VOH and high Vin yields VOL, threshold near VDD/2.
- Logic family on a fixed supply; static levels.
Computes Switching threshold from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.
Computes Pull-up resistance from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.
Computes CMOS versus TTL levels from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.
Computes Power-delay product from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.
Computes Logic fan-in from the circuit model and the stated conditions.
- Logic family on a fixed supply; static levels.