D latch

Tags

• Digital
• Electronics
• physics
• Electronics formula
• physics formula
• Sequential logic
• secuencial

Detail

Variables

• $D,J,K,T,Q$bits
• $t_{su},t_h,t_{pcq}$s
• $n$bits or modulus
• $f_{\max}$Hz.

Conditions

• D latch transparent while Enable is active (level); it is not clock-edge sampled.

Conventions

• s, Hz or dimensionless

Related formulas

• Related

  SR latch

  $$Q^+=S+\overline RQ$$
  Open formulaOpen in section

• Related

  D flip-flop

  $$Q(t_{\mathrm{clk}}^+)=D(t_{\mathrm{clk}}^-)$$
  Open formulaOpen in section

• Related

  Full adder

  $$S=A\oplus B\oplus C_{\mathrm{in}}$$
  Open formulaOpen in section

• Related

  Average propagation delay

  $$t_p=\frac{t_{pHL}+t_{pLH}}{2}$$
  Open formulaOpen in section