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Flip-flops and timing
The edge samples D; tsu and th mark the window that avoids metastability.
Key formulas
- D flip-flop
The D flip-flop samples D on the clock edge and holds Q until the next edge.
- Setup time
Setup time tsu is the window in which D must be stable before the clock edge.
- Hold time
Hold time th is the window in which D must stay stable after the clock edge.
- T flip-flop
Computes T flip-flop from the circuit model and the stated conditions.